Conventional power management techniques (e.g. setting power of a voltage region) in an integrated circuit are static in nature (e.g., determined during a design phase). One such technique may involve using a low-voltage integrated circuit to reduce an amount of power required. However, this may reduce the integrated circuit's performance (e.g., maximum operable frequency may be lower).
Another technique involves assigning multiple pre-determined power regions with power regulators (e.g., to create different voltage levels on different parts of the integrated circuit). Multiple pre-determined power regions may be formed by combining lower and/or higher voltage circuits in the integrated circuit using custom power planes. In this case, expensive custom masks and/or specialized circuits that have a fixed association with a specific voltage plane may be required.
The integrated circuit may draw more power than is needed for an application even when part or all of the device is not being fully utilized. The definition of under utilization can include operating at frequencies beyond what is needed at the requisite voltages required to support that frequency of operation to parts of the device that are idled or ‘static’ and consuming power due to leakage. Leakage (e.g., undesired current that flows when a transistor is in the “off” state; for example, MOS/CMOS devices using ultra-thin gate oxide leakage current is primarily a tunneling current across the gate oxide) is a particularly troublesome problem because it is resistant to many conventional power management techniques. Effective power management of a integrated circuit is critical to effective use of the circuit. Too much power consumed may reduce battery life of a device incorporating the integrated circuit, and/or may cause overheating of the integrated circuit.